This invention relates to semiconductor photovoltaic generators, and more specifically relates to a novel structure for a photovoltaic generator which increases its turn off speed.
Photovoltaic generators (xe2x80x9cPVGxe2x80x9ds) are well known and are shown, for example, in U.S. Pat. Nos. 4,721,986 to Kinzer; 5,549,762 to Cantarini and 5,973,257 to Cantarini and Lizotte. These devices are used to provide a turn on control signal to a semiconductor device such as a power MOSFET or the like in which the input control signal is optically isolated from the MOSFET input. The total relay is known as a photovoltaic relay (PVR). Thus, in a PVR, an input radiation signal from an LED or the like illuminates the surface of a photovoltaic generator (PVG) to produce an output gate voltage to the gate of a MOSFET or other gated switching device. Photovoltaic generators (xe2x80x9cPVGxe2x80x9ds) are well known and are shown, for example, in U.S. Pat. Nos. 4,721,986 to Kiuzer; 5,549,762 to Cantarini and 5,973,257 to Cantarini and Lizotte. These devices are used to provide a turn on control signal to a semiconductor device such as a power MOSFET or the like in which the input control signal is optically isolated from the MOSFET input. The total relay is known as a photovoltaic relay (PVR). Thus, in a PVR, an input radiation signal from an LED or the like illuminates the surface of a photovoltaic generator (PVG) to produce an output gate voltage to the gate of a MOSFET or other gated switching device.
The frequency response of the PVR is limited, at least in part, by the turn on and turn off times of the PVG. These turn on and turn off times are coupled by design trade offs wherein a structure which reduces turn off time will also increase turn on time and vice versa. For example, increasing SOI thickness reduces turn on time, but increases turn off time. Present PVG xe2x80x9cstacksxe2x80x9d employ an SOI structure in which an N type silicon layer of a thickness of about 35 microns is supported by and insulated from a thicker xe2x80x9chandlexe2x80x9d wafer. The top surface of the SOI layer contains a shallow P type diffusion so that photons entering the silicon will generate hole-electron pairs which are collected at the P/N junction to produce an output voltage. A plurality of identical insulated structures are laterally separated from one another in a common silicon chip and are connected in series to produce the desired output voltage signal.
Such stacks, using a 35 micron thick SOI layer have a turn off time (after the input light signal is removed) of about 100 xcexcs and a turn on time of about 30 xcexcs. By using a thinner SOI layer, for example, 20 microns thick, turn off time is reduced to about 50 xcexcs, but turn on time is increased to 50 xcexcs. A further reduction in SOI thickness produces a further decrease in turn off time, but a further increase in turn on time. (The above data presumes a 12 milliampere drive to the relay input.)
It would be desirable to be able to reduce turn off time without greatly increasing turn on time.
In accordance with the invention, a matrix of trenched wells extend through the thickness of the Nxe2x88x92 silicon body to provide increased recombination sites to collapse the output voltage more quickly when the illumination of the device surface is removed. By using cross-sectional area trenched wells of a non-critical area and length and by spacing them relatively far apart (relative to their width dimensions), only a small amount of the area of Nxe2x88x92 silicon is reduced so that turn on time is reduced by only a small amount. The trenched wells of the invention may be wells of any desired cross-sectional shape formed by etching trenches in the silicon; lining the trenches with a thin oxide (300 xc3x85 to 500 xc3x85 thick) and then filling the wells with intrinsic polysilicon.
By way of example, if a 35 micron SOI layer is used (giving faster turn on), a matrix of 3 xcexcmxc3x973 xcexcm trenched wells spaced 10 xcexcm apart (center-to-center) will reduce the Nxe2x88x92 silicon area by less than 10%, thus limiting the sacrifice of turn on speed. Further, the SOI layer thickness can be increased, for example, to 50 xcexcm so that the loss in turn on speed due to the trenched wells would be gained back in the additional 10% absorption gained from the increased SOI thickness.
The novel use of trenched wells should also be considered in combination with other factors that influence turn off time in PVGs. Thus, there are 4 items that, in combination with one another, improve the overall response time performance of the microelectronic relay. The 4 items include 1) control circuitry, 2) SOI thickness, 3) buried implant layer, and 4) the trenched wells. These items are described in more detail in the following:
1) Control Circuitry
By experimentation, it has been shown that the xe2x80x9cBOSFETxe2x80x9d control circuitry (U.S. Pat. No. 4,721,986: FIG. 14) is the best circuitry for xe2x80x9cfast turn offxe2x80x9d response time. This turn off time exceeds the response time of the control circuitry of U.S. Pat. No. 5,549,792 by about 50%, depending on the SOI thickness. The control circuitry has no impact on the turn on time but significantly improves the turn off time.
2) SOI Thickness
A thinner SOI thickness reduces the turn off time, but in exchange, increases turn on time due to a higher short circuit current produced from the thicker SOI layer. The best combination of turn on to turn off time has been found to be the thinner SOI thickness of 20 xcexcm (best range 15-25 xcexcm). A reduction of about 30 to 35% faster turn off is gained by using the thinner SOI while only reducing the turn on time by about 15 to 20%.
3) Buried Implant Layer
When comparing the buried N+ layer (at the bottom of the silicon layer), the turn off time had about 30% improvement, with no impact on turn on time.
4) Trenched Wells
A 40-50% reduction in turn off time is achieved over the standard cell (no trenched wells) by adding the trenched wells while only reducing the turn on time by 15-20%. The best percent reduction in silicon (due to the trenched wells) to achieve the best combination of turn on versus turn off time is in the region of 10% to 20% reduction of the cell area.
In Summary
By combining all 4 options, the response time can be significantly improved. This improvement can be seen in the following table as a 4 times improvement in the frequency response over prior art devices.